Engineering Plan Engineering Plan SC312 Final hobble 11/7/04 *Names* We plan to utilise the elemental multi-cycle processor design as shown in the textbook, as about as pipelining and jump and link. The toughest part of this design testament be the datapath control, for which we volition be using a FSM. The ALU volition implement add, sub, and, or, sll, and slt functions though a separate block is typically used for shift operations, we felt that putting sll and srl in the ALU would castrate our design. All other basic functions (lw, sw, lui, beq, bne, j) will be go for as show in the textbook.
The processor will expect two main stages: load instructions into store and implement instructions. Special instruction codes will be defined as stall and stop execution to work in hamlet with the FSM. The global reset will set all recollection and registers to 0, and put the FSM in load instructions mode. We would standardised to use one memory module to store both instruct...If you want to get a full essay, order it on our website:
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